When a data source on an integrated circuit requires access to write to a target memory, it will normally instruct the processor via an initiator on a word-by-word basis. A source may be a block of memory, and the initiator is the logic which specifies the access required for that memory. The instruction to write to the memory contains the memory address to which the data word is to be written, and the word is then written to that memory location. Then, the next word is taken and a new instruction specifies the next memory location, and the next data word is written to its respective location. This continues until all the data has been written to memory.
With a large block of data to be written, this is a slow process. When a block of data has to be written to a contiguous section of memory, a direct memory access (DMA) can be used. For this, the instruction specifies only the location of the first word to be written, and subsequent data words can be simply streamed to successive subsequent locations in memory. This is much quicker than the normal method of writing the data word-by-word. However, it requires the data source to indicate to the memory that DMA is being used. Even if the address is included in every subsequent word, a target memory can place all DMA accesses in a special buffer separate from other data on the same part. This allows more efficient transfers to the memory. If the source is on one integrated circuit device (chip) and the target on another, then a pin is required to convey a DMA access signal from the source to the target. A source may be a processor or memory and an initiator is usually provided to initiate access from the source. The terms initiator and source are used equally to describe what may be the same components.
If two initiators are present on the source chip and both require direct memory access to a memory on another chip, then two DMA access pins are required on the chip to convey a respective DMA access signal from the respective source to the memory. In general, a DMA access pin is required for each initiator combination, so if there are two sources on the source chip and two target memories on the memory chip then two DMA access pins are required on the source chip.
This is illustrated in FIG. 1 which shows a prior art DMA system in which two initiators on a source chip 110 can access two memories on a target chip 112. The source chip 110 has a first initiator A 114 and a second initiator B 116. Two initiators are shown for simplicity, but there may often be more than two, and six would not be uncommon. Each initiator has a data and address bus output 118. A bus interface 120 is also provided on the source chip 110 and has a bus input 122 and a bus output 124. A data and address bus 126 connects the data and address output 118 of the first source 114, the data and address bus output 118 on the second source 116, and the bus input 122 of the bus interface 120. Bus output pins 128 are provided on the chip 110 for external connection to the target chip 112. The bus output pins 128 are coupled to the bus output 124 of the bus interface 120 by a bus 130.
The target chip 112 has bus input pins 132 connected by external connections 131 to the bus output pins 128 on the source chip 110. The bus input pins 132 are connected by a bus 134 to the input 136 of a bus interface 138. The bus output 140 of the bus interface 138 is coupled to a bus 142 which is connected to the inputs 144 of each of two targets, namely a destination X 146 and a destination Y 148.
The target is a port which is coupled to a random access memory (RAM) which may be on the target chip 112 or may be external to it. The target provides a port or channel to the memory and the target port and the memory itself together form a memory circuit. The target may comprise an interface to an external microprocessor, and may include a read-ahead buffer. The bus interfaces 120,138 are described for convenience as having inputs and outputs since they are used in that sense during a DMA write access, though in fact their ports may be bidirectional.
When normal write operations are required, the selected initiator 114 or 116 provides the data and memory address location over the bus 126 to the bus interface 120. This is conveyed by bus 130, pins 128, external connections 131, pins 132, and bus 134 to the bus interface 138. The bus interface 138 then conveys the data and address onto the bus 142 and to the appropriate target 146,148. The associated memory is then written with the data in accordance with the address instruction. This is then repeated for subsequent data words to be written to the memory.
For DMA access from the sources 114,116 to the targets 146,148, it is necessary for the sources to indicate to the required target that a DMA access is to take place. Thus the initiator 114 has a first DMA access output 150 onto which a DMA access signal is applied when a DMA access is required to target 146. The output 150 is coupled by a line 152 to a pin 154 on the chip 110. The pin 154 is connected by an external connection 156 to a pin 158 on the chip 112 which is connected by a line 160 to a DMA access signal input 162 on the destination 146. When the source 114 requires DMA access to the target 146, the output 150 is asserted and a signal is applied to the target 146 to tell it to expect direct memory access to take place.
Initiator 114 similarly has a DMA access signal connection to the target 148. This is similar to the connection already described, and includes a second DMA access output 164 on initiator 114, a second pin 166 on the chip 110, a second pin 168 on the chip 112, and a DMA access signal input 170 on the second destination 148. The second initiator 116 is similarly connected to the targets 146 and 148. The second initiator 116 has an output 172 connected to a pin 174 on chip 110, in turn connected to a pin 176 on chip 112 connected to an input 178 on destination 146. The second source 116 also has an output 180 connected to a pin 182 on the source chip 110, in turn connected to a pin 184 on the target chip 112 connected to an input 186 on target 148.
With this prior art arrangement a total of two DMA access signal pins 154 and 182 are required on the source chip 110.
A second prior art DMA system is shown in FIG. 1A. For simplicity, only those parts relevant to a DMA access are shown and like components are given the same reference numerals as before. Two initiators requiring DMA access, initiator A 114 and initiator B 116 are present on the source chip 110 and have respective DMA access outputs 150, 180 to indicate when DMA access is required. An OR gate 600 receives these two outputs and provides a DMA access signal to DMA pin 154 which thereby indicates that DMA access is required either by initiator A or initiator B to the destination X 146 on the target chip 112. This is via DMA input pin 158 and input 162 on the target chip 112.
While this proposal reduces the number of pins required on the source device, it is only applicable to the case of a single DMA, it is only applicable to the case of a single DMA channel in the target chip 112 and two DMA initiators in the source chip 110. If three initiators are present on the source device, then three pins would be required.
A third previously proposed DMA system is shown in FIG. 1B. Again, only those components relevant to DMA access are shown and the same reference numerals are used as before. In this example, there are three initiators requiring DMA access labelled initiator A 114, initiator B 116 and initiator C 117, on the source chip 110, each having a respective DMA output 150, 180, 181. The output of initiator A connects to pin 154, the output of initiator B to pin 182 and the output of initiator C to pin 183. Now, as each initiator may require DMA access to either of the destinations X 146 or Y 148, external connections 157 are provided to a pair of OR gates 602, 604.
Each DMA pin 154, 182, 183 is connected by the external connections 157 to each OR gate 602, 604 so that each OR gate has three inputs. The output of the first OR gate 602 is asserted to DMA input pin 602 when any of the initiators 150, 180, 181 require DMA access to destination X 146. Similarly, the output of the second OR gate 604 is asserted to DMA input pin 169 when any of the initiators 150, 180, 181 require DMA access to destination Y 148. As can be seen, this arrangement requires a total of five pins; three on the source chip 110 and two on the destination 112. Other possibilities include placing the OR gates on the source device 112 thereby reducing the number of output pins required to two.